From a system architecture perspective, routers can be categorized into multiple generations: first-generation single-bus single-CPU routers, second-generation single-bus master-slave CPU routers, third-generation single-bus symmetric multi-CPU routers, fourth-generation multi-bus multi-CPU routers, fifth-generation shared-memory architecture routers, sixth-generation crossbar switch architecture routers, and cluster-based routers, among others.
A router comprises four key elements: input ports, output ports, a switching fabric, and a routing processor.
Input ports serve as the entry point for physical links and incoming packets. Ports are typically provided by line cards, with a single line card generally supporting 4, 8, or 16 ports. An input port performs several functions.
鈼?The first function is performing data link layer encapsulation and decapsulation.
鈼?The second function is looking up the destination address of an incoming packet in the forwarding table to determine the destination port (known as route lookup). Route lookup can be implemented using general-purpose hardware or by embedding a microprocessor on each line card.
鈼?Third, to provide QoS (Quality of Service), the port must classify received packets into several predefined service levels.
鈼?Fourth, the port may need to run data link protocols such as SLIP (Serial Line Internet Protocol) and PPP (Point-to-Point Protocol) or network-level protocols such as PPTP (Point-to-Point Tunneling Protocol). Once the route lookup is complete, the switching fabric must deliver the packet to its output port. If the router employs output-side queuing, several output ports share the same switching fabric. In this case, a final function of the input port is participating in arbitration protocols for shared resources, such as the switching fabric.
The switching fabric can be implemented using a variety of technologies. The most commonly used switching fabric technologies to date are buses, crossbar switches, and shared memory. The simplest switch uses a single bus to connect all input and output ports. The drawback of a bus-based switch is that its switching capacity is limited by the bus capacity and the overhead incurred by shared bus arbitration.
A crossbar switch provides multiple data paths through its switching elements. A crossbar with N×N crosspoints can be thought of as having 2N buses. If a crosspoint is closed, the data on the input bus is available on the output bus; otherwise, it is not. The closure and opening of crosspoints are controlled by a scheduler, which, therefore, limits the speed of the switching fabric.
In a shared-memory router, incoming packets are stored in shared memory, and only packet pointers are switched. This increases switching capacity; however, the switch speed is limited by the memory access speed. While memory capacity can double every 18 months, memory access time improves by only 5% per year, which is an inherent limitation of shared-memory switching fabrics.
Output ports store packets before they are transmitted onto the output link and can implement complex scheduling algorithms to support requirements such as priority handling. Like input ports, output ports must also support data link layer encapsulation and decapsulation, as well as numerous higher-level protocols.